intal. tel 82527 SERIAL COMMUNICATIONS CONTROLLER CONTROLLER AREA NETWORK PROTOCOL Automotive m Supports CAN Specification 2.0 @ Programmable Bit Rate - Standard Data and Remote Frames - Extended Data and Remote Frames m Programmable Clock Output Flexible Interrupt Structure m Programmable Global Mask . - Standard Message Identifier Flexible Status Interface Configurable Output Driver - Extended Message Identifier m 15 Message Objects of 8-Byte Data Configurable Input Comparator: Two 8-Bit Bidirectional I/O Ports Length 44-Lead PLCC Package - 14 Tx/Rx Buffers - 1 Rx Buffer with Programmable Mask 44-Lead QFP Package Pinout Compatibility with the 82526 m Flexible CPU Interface - 8-Bit Multiplexed - 16-Bit Multiplexed - 8-Bit Non-Multiplexed (Synchronous/Asynchronous) - Serial Interface The 82527 serial communications controller is a highly integrated device that performs serial communication according to the CAN protocol. It performs all serial communication functions such as transmission and reception of messages, message filtering, transmit search, and interrupt search with minimal interaction from the host microcontroller, or CPU. The 82527 is Intel's first device to support the standard and extended message frames in CAN Specification 2.0 Part B. It has the capability to transmit, receive, and perform message filtering on extended message frames. Due to the backwardly compatible nature of CAN Specification 2.0, the 82527 also fully supports the standard message frames in CAN Specification 2.0 Part A. The 82527 features a powerful CPU interface that offers flexibility to directly Interface to many different CPUs. It can be configured to interface with CPUs using an 8-bit multiplexed, 16-bit multiplexed, or 8-bit non-mulfi- plexed address/data bus for Intel and non-Intel architectures. A flexible serial interface (SP) is also available when a parallel] CPU interface is not required. The 82527 provides storage for 15 message objects of 8-byte data length. Each message object can be configured as either transmit or receive except for the last message object. The last message abject is a receive-only buffer with a special mask design to allow select groups of different message identifiers to be received. The 82527 alsc implements a global masking feature for message filtering. This feature allows the user to globally mask any identifier bits of the incoming message. The programmable global mask can be used for both standard and extended messages. The 82527 PLCC offers hardware, or pinout, compatibility with the 82526. It is pin-to-pin compatible with the 82526 except for pins 9, 30, and 44. These pins are used as chip selects on the 82526 and are used as GPU interface mode selection pins on the 82527. The 82527 is fabricated using Intel's reliable CHMOS III 5V technology and is available in either 44-lead PLCC | or 44-lead QFP for the automotive temperature range {(40C to + 125C). *Other brands and names are ihe property of their respective owners. information in this document is provided In connection with Intel products, Intel assurnas no liabildy whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products, intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT INTELCORPORATION, 2004 July 2004 Order Number. 272250-007., 82527 | intel. Port 1 Port 2 hb 1X0 Addrass/ i > Xi Data Bus CAN Controlier cPU Interface K RAM HM RXO Control Logic Bus Hee RX LL, CLKOUT Mode 0 Modo 1 CLKOUT 272250-1 Figure 1.82527 Block Diagram = ad 0 8 3 log = a ONL ta ss Ew Or M gam +t 0 w ao - oan oO aa aga ef tf f tft > EE fF ff HDOnoOeroOe Oooo 6 5 4 3 2 1 44435 42 41 40 Cane /WRLi)/(R/ WH) D7 3910) an? cs# [3 38] Pi./aDs psacko# [3 37 (71 P1.7/ap8 WRH#/P2.7 DR10 3610] P1.2/ap16 INT#/P2.6 E11 xx82527 35(1 P1.3/AD!1 P2.5 [#12 3407] Pi.4/AD12 p2.4 Chis TOP VIEW 33 (0) Pt.5/ab13 p23 Chi 32 FI Pt.6/abi4 p29 Cis 31 (71 P1.7/A015 P2.4 0016 3010] Move 1 P2.0 [17 29 [CF RESET# 18 19 20 71 22 23 24 25 26 27 2B HUOOUUOGGUDO oO 5359 322 aA QE SB ee PES YORE SS ed oO go MN 2 oz = a2 = Li > ee ~ 272250-2 Figure 2.44-Pin PLCC Package82527 = x n $ 3 ue eo = a ae tl ~ ao ou @r a 5 Om 4 o3a2a4 4 Of BEGaoaand et ttt Fr Ft ttt DRED OOOOAR aH f 4443 42 4140 39 38 37 56 35 34 Cyr /WRL#)/(R/ WH) 1 33 [J aD? cs# E]2 32 J P1.0/AD8 osacko# [7] 3 34 Eo) P1.1/an9 WRHA/P2.7 [4 30 FI P1.2/ab10 INT#/P2.6 [95 2527 297 Pt.3/api1 p2.s C86 xx825 28 [0] P1.4/an12 p24 C7 Top View 27 P1.5/aD13 p2.3 Cha 26 (1 P1.6/ADi4 pz.2C}3 25 CUP1.7/aDI5 P21 2) 10 24 [OF MODE1 P2.0 Di: 23 [OF RESET# 12 13 14 15 16 17 8 19 20 24 22 LGUEUUUUUUUUEU 59 82 2 AR A258 Ee wee Grr oS Oe 2 oO = ao x ~ go a * i E oe 272250-15 Figure 3. 44-Pin QFP Packageso527 intel. PIN DESCRIPTION The $2527 pins are described in this section. Table 1 presents the legend for interpreting the pin types. Table 1. Pin Type Legend Symbol Description t Input only pin 0 Output only pin vO Pin can be either input or output PIN DESCRIPTIONS Pin Name ;} Pin Type Pin Description Vssi Ground ; GROUND connection must be connected externally to a Vss board plane. Provides digital ground. Vss2 Ground GROUND connection must be connected externally to a Ves board plane. Provides ground for analog comparator. Vec Power POWER connection must be connected externally to +5V DC. Provides power for entire device. XTALI | Input for an external clock. XTAL1 (along with XTAL2) are the crystal connections to an internal oscillator. XTAL2 0 Push-pull output from the internal oscillator. XTAL2 (along with XTAL1) are the crystal connections to an internal oscillator. If an external oscillator is used XTAL2 must be floated, or not be connected. XTAL2 must not be used as a clock output to drive other CPUs. CLKOUT 0 Programmable clock output. This output may be used to drive the oscillator of the host microcontroller. RESET# I Warm Reset: (Vcc remains valid while RESET# is asserted), RESET# must be driven to a valid low level for 1 ms minimum, Cold Reset: (Vcc is driven to a valid level while RESET+# is asserted), RESET# must be driven low for 1 ms minimum measured from a valid Vcc level. No falling edge on the reset pin is required during a cold reset event. CS# I A low level on this pin enables CPU access to the 82527 device. INT # 0 The interrupt pin is an open-drain output to the host microcontroller. Ve/2 is Vec/2) oO the power supply for the ISO low speed physical layer. The function of this pin is determined by the MUX bit in the CPU Interface Register (Address 02H) as follows: MUX = 1: pin 24 (PLCC) = Vec/2, pin 11 = INT# MUX = 0: pin 24 (PLCC) = INT# RxX0 l Inputs from the CAN bus line(s) to the input comparator. A recessive level is RX1 I read when RXO > RX1.A dominant level is read when RX1 > RXO. When the CoBy bit (Bus Configuration register} is programmed as a ~1", the input comparator is bypassed and RXQ is the CAN bus line input. TXO Oo Serial data push-pull output to the CAN bus line. During a recessive bit TX0 is TX oO high and TX 1 is low. During a dominant bit TX0 is low and TX is high.intel. 82527 Pin Name Pin Type Pin Description ADO/AO/ICP I-11 Address/Data bus in 8-bit multiplexed made. ADTATICP VO-I-| Address bus in 8-bit non-multipiexed mode. AD2/AZICSAS /O-F- Low byte of A/D bus in 16-bit multiplexed mode. ADS/A3/STE vO-| tn Serial Interface mode, the following pins have the following meaning: AD4/A4/MOSI HO-I-4 ADO: ICP Idle Clock Polarity ADSIA5 HO-| ADi: CP Clock Phase AD6/AG/SCLK O-1-E AD2:; GSAS Chip Select Active State ADTIA? O-I AD3: STE Syne Transmit Enable AD6: SCLK Serial Clock Input AD4: MOS! Serial Data Input AD8/DO/P'1.0 0-0-0 High byte of A/D bus in 16-bit multiplexed mode. ADS/D1/P 1.4 170-0-1/0 Data bus in 8-bit non-multipiexed made. AD1IO/D2/P 1.2 0-0-0 Low speed I/O port. P1 pins in 8-bit multiplexed mode and serial mode. AD11/D3/P1.3 0-0-0 Port pins have weak pullups until the port is configured by writing to 8FH AD12/D4/P1.4 | VO-0-"O | and AFH. AD13/B5/P1.5 VO-0-1/0 AD14/D6/P1.6 O-O-1/0 AD15/D7/P1.7 VO-O-V/0 P2.0 fO P2 in ail modes. P2.1 VO P2.6is INT# when MUX = 1 and is open-drain. P2.2 vO P2.7 is WRH# in 16-bit multiplexed mode. P2.3 vO P2.4 vO P2.5 tO P2.6/INT # 0-0 P2.7ANRH # VO-E Moded ] These pins select one of the four parallel interfaces. These pins are Mode1 i weakly held low during reset. Mode1 Moded 0 0 8-bit multiplexed B Intel 0 0 Serial Interface mode entered when RD# = 0, WR+# = 0 upon reset. 6 1 16-bit multiplexed B Intel 1 0 8-bit multiplexed D non-intel 1 1 8-bit non-multiplexed ALE/AS I-1 ALE used for Intel modes. AS used for non-Intel modes, except Mode 3 this pin must be tied high. RD# I RB# used for Intel modes. E 1 E used for non-Intel modes, except Mode 3 Asynchronous this pin must be tied high. WR#AARL # | WR# in 8-bit Intel mode and WRL# in 16-bit Intel mode, RAW # I RAV # used for non-Intel modes. READY Oo READY is an output to synchronize accesses from the host MISO oO microcontroller to the 62527, READY is an open-drain output te the host microcontroller. MISO is the serial data output for the serial interface mode. DSACKO# 0 DSACKG# is an open-drain output to synchronize accesses from the host microcontroller to the 82527.